With continuous development of the power electronics technology, Pulse Width Modulation (PWM) has gradually become a mainstream control manner for a power electronic converter, and is increasingly widely applied to Uninterruptible Power Supply (UPS), a photovoltaic inverter, a wind energy converter and a motor converter.
Inverters may be classified into a two-level inverter, a three-level inverter, a five-level inverter and a multi-level inverter, in terms of the number of levels of a phase voltage outputted by a PWM modulation inverter. The five-level inverter and the multi-level inverter are more difficult to be implemented due to their complexity. Presently, the two-level inverter and the three-level inverter are mainly used in an industry.
The two-level inverter is easier to be implemented and has a lower cost, but a switch device with a high voltage resistant level needs to be selected since the switch device is to bear a whole bus voltage stress. A switch loss of the two-level inverter is greater, thereby limiting improving of a PWM switch frequency. Harmonic contents of an output voltage are high in the two-level inverter, resulting in a greater volume and loss of an output filter.
Output levels of the three-level inverter are more than that of the two-level inverter, and a voltage stress born by the switch device in the three-level inverter is a half of that of the two-level inverter, therefore a switch device with a lower voltage resistant level may be selected. A switch loss of the switch transistor is lower, harmonic contents of the output voltage are lower than that in the two-level inverter, therefore the volume of the output filter may be reduced.
A common three-level topology is a conventional diode 3 Level-Neutral Point Clamped (3L-NPC) topology, a schematic structural diagram of which is shown in FIG. 1. As shown in FIG. 1, the diode 3L-NPC topology includes: a first bus capacitor C1, a second bus capacitor C2 and an inverter circuit. The C1 and C2 are connected in series between a positive direct current bus and a negative direct current bus, and a serial point of the C1 and C2 is grounded. The inverter circuit includes a first switch transistor S1, a second switch transistor S2, a third switch transistor S3 and a fourth switch transistor S4, and the S1, S2, S3 and S4 are sequentially connected in series between the positive direct current bus and the negative direct current bus in a same direction. Further, each of the switch transistors S1, S2, S3 and S4 is anti-parallel connected to a diode, i.e., a first diode D1, a second diode D2, a third diode D3 and a fourth diode D4 respectively. The inverter circuit further includes a fifth diode D5 and a sixth diode D6. The D5 and D6 are connected in series in a same direction, one terminal of series-connected D5 and D6 is connected to a serial point of S1 and S2, the other terminal is connected to a serial point of S3 and S4, and a serial point of the D5 and D6 is connected to a serial point of the C1 and C2. The diode 3L-NPC topology further includes a filtering circuit. The filtering circuit may include an inductor and a capacitor connected in series, one terminal of the filtering circuit may be connected to a serial point of the S2 and S3, and the other terminal of the filtering circuit is grounded.
Due to existence of the clamped diode and an internal clamped switch device, each phase of circuit may output three levels, i.e., Vdc/2, 0, −Vdc/2 (wherein Vdc is a direct current bus voltage), and a line voltage may obtain an output voltage of 5 levels. For example, when the switch transistors S1 and S2 are turned on, the diode 3L-NPC topology may output a level of Vdc/2 (as shown in FIG. 2(a), a thick line indicates that the line is turned on); when the switch transistors S2 and S3 are turned on, the diode 3L-NPC topology may output a level of 0 (as shown in FIG. 2(b)); and when the switch transistors S3 and S4 are turned on, the diode 3L-NPC topology may output a level of −Vdc/2 (as shown in FIG. 2(c)). Therefore, the switch transistors S1 and S4 mainly bear switch losses, and S2 and S3 mainly bear turned-on losses.
That is, from FIG. 2(a), FIG. 2(b) and FIG. 2(c), the 3L-NPC topology has a unique zero level switch state; based on a direction of a load current, when the current direction is positive, the current can flow only through the switch transistor S2 and the diode D5 on the middle of the upper side; and when the current direction is negative, the current can flow only through the switch transistor S3 and the diode D6 on the lower side. The direction of the current outputted by a middle point of a bridge arm is uniquely determined by the load current, therefore the current is uncontrollable when the zero level is outputted, thereby resulting in unbalance of losses of power devices.
In addition, when a level of Vdc/2 is outputted, the switch transistors S3 and the switch transistor S4 are connected in series to bear the whole bus voltage. Due to device difference or other factors, the two switch devices generally have non-uniform voltages, thereby resulting in that one switch device bears a bus voltage higher than Vdc/2 or much higher, and an over-voltage damage may be caused when a voltage across the device is too high in a severe case.
In order to solve the above problems, active controllable devices, i.e., a fifth switch transistor S5 and a sixth switch transistor S6, may be connected in parallel to the clamped diodes D5 and D6 in the conventional 3L-NPC topology circuit respectively, to form a 3 Level-Active Neutral Point Clamped (3L-ANPC) topology shown in FIG. 3. The topology can completely solve the problem of loss unbalance and non-uniform voltage of the power devices in the diode multi-level-neutral point clamped topology.
In practice, it is found by the applicant that, although the 3L-NPC topology and the 3L-ANPC topology have been widely applied in the field of power electronics, the switch loss and an on-state loss of the switch devices thereof are great, therefore efficiency is not high. In view of this, it is still a critical technical problem that how to improve efficiency of the three-level inverter.